Generally, tungsten, aluminum, or copper is used for a metal interconnection in a semiconductor device. Copper has a lower resistance and superior reliability than aluminum or tungsten. The research and development has focused on methods for using copper for metal interconnection as an alternative to aluminum.
However, it is difficult to perform a dry-etch process on copper than on tungsten or aluminum. Thus, dual damascene methods have been developed which enable simultaneous formation of a contact plug and an interconnection with copper, without performing a dry-etch process. In a dual damascene process, a contact hole and a groove are formed through an interlayer dielectric layer, and then the contact hole and the groove are filled with copper. Thus, a contact hole and an interconnection are simultaneously formed. A conventional method of forming a dual damascene structure will now be explained with reference to FIG. 1, which illustrates a cross-sectional view of a semiconductor device having a dual damascene structure formed according to a conventional method.
Referring to FIG. 1, a bottom layer 11 and an interlayer dielectric layer 12 are sequentially formed on a semiconductor substrate 10. The interlayer dielectric layer 12 is patterned to form a bottom-recessed region and the bottom-recessed region is filled with a conductive material to form a bottom interconnection 13. A first etch stopping layer 15, a bottom intermetal dielectric layer 17, a second etch stopping layer 19, and an upper intermetal dielectric layer 21 are sequentially stacked on an entire surface of a semiconductor substrate 10 having the bottom interconnection 13 and the interlayer dielectric layer 12. The first and second etch stopping layer 15 and 19 may be formed of a silicon nitride (Si3N4), and the upper and bottom intermetal dielectric layer 21 and 17 may be formed of an oxide material. By using a photoresist pattern, the upper intermetal dielectric layer 21, the second etch stopping layer 19, and the bottom intermetal dielectric layer 17 are sequentially patterned to form a first recessed region 22 exposing the first etch stopping layer 15. By using another photoresist pattern, the upper intermetal dielectric layer 21 is etched to form a second recessed region having a shallower depth and wider width than the first recessed region 22 and a portion of the second etch stopping layer 19 is exposed. A gas comprising fluorocarbon is used as an etch gas. Then, the exposed second etch stopping layer 19 is patterned to expose a portion of the bottom intermetal dielectric layer 17, and the first etch stopping layer 15 is simultaneously patterned to expose the bottom interconnection 13.
In a conventional etch process using a conventional etch gas, there is a little etch selectivity between the first etch stopping layer 15 and the upper intermetal dielectric layer 21. Thus, when the upper intermetal dielectric layer 21 is etched to form the second recessed region 23, the first etch stopping layer 15 is also etched. Furthermore, the bottom interconnection 13 is etched. At this time, the bottom interconnection 13 reacts with the etch gas to form a by product P.
FIGS. 2A through 2C are cross-sectional views showing a method of forming a dual damascene structure according to another conventional method.
Referring to FIG. 2A, to solve the problem discussed in view of FIG. 1, a bottom anti-refractive coating 25 is conformally formed to protect the bottom interconnection 13 and the first etch stopping layer 15 on an entire surface of a semiconductor substrate 10 where the first recessed region 22 is formed.
Referring to FIG. 2B, a photoresist pattern PR is formed on the bottom anti-refractive coating 25. The bottom anti-refractive coating 25 is anisotropically etched by using the photoresist pattern PR to expose the upper intermetal dielectric layer 21. By anisotropically etching the bottom anti-refractive coating 25, a first bottom anti-refractive coating pattern 25a remains under the photoresist pattern PR, and a second bottom anti-refractive coating pattern 25b remains covering a bottom and a portion of a sidewall of the first recessed region 22. A top portion of the second bottom anti-refractive coating pattern 25b can be higher than the second etch stopping layer 19, as shown in FIG. 2B.
Referring to FIG. 2C, by using the photoresist pattern PR, the upper intermetal dielectric layer 21 is anisotropically etched to form a second recessed region 23 having a shallower depth and a wider width than the first recessed region 22 and exposing the second etch stopping layer 19. When the upper intermetal dielectric layer 21 is anisotropically etched in order to form the second recessed region 23, an oxide fence 21a is formed on the second etch stopping layer 19 due to the second bottom anti-refractive coating pattern 25b. The oxide fence 21a creates problems in subsequent processing. For example, in a case of forming a barrier metal layer in a subsequent process, it is difficult to form a barrier metal layer along a profile of the second recess region 23 due to the oxide fence 21a. Thus, a method of forming a dual damascene structure is needed to protect the bottom interconnection 13 without forming the oxide fence 21a. 